verilog - The counter counts strangly -

my code describes fsm control traffic light. there 4 states, each different duration.

whenever counter equals 1, counter needs 1 more clock change next value. example, @ state1, counter programmed count 4 1. every value should take 1 clock change next, when does, state changed next state. when counter equals 1, takes 2 clocks change.

my program follows. counter implemented @ bottom of block:

module hw3(times,a,b,clk,rst,ihand,ichang,s1);  input clk,rst; output reg [2:0]a,b; wire oclk;//new freq reg [2:0] count1,count2,count3,count4;//count times reg  [2:0]times; reg temp;//control switch  parameter [2:0]state1=3'd0,state2=3'd1,state3=3'd2,state4=3'd3;  always@(posedge clk or negedge rst  )     begin                    if(!rst)                     begin                         s1<=state1;                         a<=3'b0;                         b<=3'b0;                         count1<=3'd4;                         count2<=3'd2;                         count3<=3'd3;                         count4<=3'd2;                         temp<=1'b1;                     end                 else                     begin                         if(temp==1)                             begin                                 temp<=1'b0;                                 case(s1)                                     state1:                                         begin                                             times<=count1;                                             a<=3'b001;                                             b<=3'b100;                                             s1<=state2;                                         end                                     state2:                                         begin                                             times<=count2;                                             a<=3'b010;                                             b<=3'b100;                                             s1<=state3;                                                      end                                     state3:                                         begin                                             times<=count3;                                             a<=3'b100;                                             b<=3'b001;                                             s1<=state4;                                          end                                     state4:                                         begin                                             times<=count4;                                             a<=3'b100;                                             b<=3'b010;                                             s1<=state1;                                         end                                     default:                                         begin                                             a<=3'b000;                                             b<=3'b000;                                         end                                     endcase                             end                          else                             begin                                 if(times>1)                                     times<=times-1;                                 else if(times==1)                                     begin                                         temp<=1'b1;//can't count averagely                                      end                             end                     end      end  endmodule  

modify code @ bottom of clock as:     if(times>2)  times<=times-1;          else if(times==2)                  begin                          times=times-1;                          temp<=1'b1;//can't count averagely                        end          

just let times counts 2 ,because if let count 1, program again enter if

block in next clock doesnt change value of times ,and make value of times=1 unchanged

for 1 more clock