caching - Is Translation Lookaside Buffer (TLB) the same level as L1 cache to CPU? So, Can I overlap virtual address translation with the L1 cache access? -

i trying understand whole structure , concepts caching. use tlb fast mapping virtual addresses physical addresses, in case if use virtually-indexed, physically-tagged l1 cache, can 1 overlap virtual address translation l1 cache access?

yes, that's whole point of vipt cache.

since virtual addresses , physical 1 match on lower bits (the page offset same), don't need translate them. vipt caches built around (note limits number of sets can use, can grow associativity instead), can use lower bits lookup in cache before found translation in tlb.

this critical because tlb lookup takes time, , l1 caches designed provide bw , low latency possible avoid stalling much-faster execution.

if miss tlb , suffer greater latency (either level2 tlb or, god forbid, page walk), it's less critical since can't cache lookup until compare tag, few cycles did save in tlb hit + cache hit case should common case on many applications, that's considered worthy optimize , align pipelines for.