memory - Creating large dual-port RAM in VHDL -

i trying generate ram store editable bitmap rudimentary paint program in vhdl. this, 1 set of i/o takes address of current pixel , outputs stored pixel color. other set takes address of pixel written , color data input. because of size of display, needs 1megx12bit dual-port ram. however, synthesis infers latches starting @ 2^13th address leading me believe running out of resources. can ram work?

here's code (note input tool not used , removed):

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;  entity dualram_custom port (     addr1  : in  std_logic_vector(19 downto 0);     d_in2  : in  std_logic_vector(11 downto 0);     addr2  : in  std_logic_vector(19 downto 0);     we2    : in  std_logic;     tool   : in  std_logic_vector(3 downto 0);     clr    : in  std_logic;     clk    : in  std_logic;     d_out1 : out std_logic_vector(11 downto 0) );       end dualram_custom;  architecture behavioral of dualram_custom     type ram_type array(0 1048575) of std_logic_vector(11 downto 0);     signal ram : ram_type := (others => (others => '0')); begin      process(clk)     begin         if((clk'event) , (clk = '1'))             d_out1 <= ram(to_integer(unsigned(addr1)));              if ((we2 = '1') , (clr = '0'))                 if (clr = '1')                     ram(to_integer(unsigned(addr2))) <= x"000";                 else                     ram(to_integer(unsigned(addr2))) <= d_in2;                 end if;             end if;         end if;     end process; end behavioral; 

you need @ type of ram parts support. 1 thing may causing problems initialization of ram. technologies not support reset on rams. pre-load during power up.

signal ram : ram_type := (others => (others => '0')); 

also note clr logic little odd (as noted bill lynch). note functional part of ram on chip not have form of reset on it, logic on front end of ram. mix in coding style , might result in synthesis tool not support. recommend @ least temporarily removing clr functionality, working without , experiment re-adding it.

i recommend using variable ram rather signal signal ram of size implementing may result in simulation running slower variable.

the following code true dual port ram. have synthesized both xilinx , altera. has little more features need, remove parts don't need , give try. may take little experimenting tools synthesizing want.

architecture rtl of dpram_riro_rf_1024_var begin   memproc : process (clka, clkb)      type memtype array (0 1023) of std_logic_vector(7 downto 0) ;     variable mem : memtype ;   begin     if rising_edge(clka)            dataouta <= mem(to_integer(unsigned(addra))) ;        if writea = '1'          mem(to_integer(unsigned(addra))) := dataina ;        end if ;     end if ;      if rising_edge(clkb)            dataoutb <= mem(to_integer(unsigned(addrb))) ;        if writeb = '1'          mem(to_integer(unsigned(addrb))) := datainb ;        end if ;     end if ;    end process ;  end rtl ; 

once works, sure @ how many resources uses have noticed of working rams ended using 2x resources needed until got coding right.